Model circuits used in Berkeley short-channel IGFET model (BSIM) circuit simulation are conventionally known (see, e.g., Japanese Laid-Open Patent Publication Nos. 2003-68756 and 2006-119716). In such a model circuit, a PN-junction diode formed in a metal-oxide-semiconductor field-effect transistor (MOSFET) is substituted with a current source and a capacitive element. An example will be described of the PN-junction diode formed in a MOSFET and the substitution of the PN-junction diode by a current source and a capacitive element.
FIG. 15 is an explanatory diagram of an example of a vertical structure of a conventional transistor. FIG. 15 depicts a vertical structure 1500 of an N-channel MOSFET (hereinafter, “NMOS”), and a depletion layer 111 that is formed when voltage is applied to the NMOS. The vertical structure 1500 includes a gate electrode 101, a gate insulating film 102, a source region 107, a drain region 108, a substrate 109, and device isolation regions 110.
The substrate 109 is a P-type substrate. A “substrate region” refers to the substrate 109 in the NMOS. The source region 107 is an N-type region and is formed by source regions 103 and 105, the source region 103 being deeper from the surface of the source region 107 than the source region 105. The drain region 108 is an N-type region and is formed by drain regions 104 and 106, the drain region 104 being deeper from the surface of the drain region 108 than the drain region 106.
The depletion layer 111 is formed in the vertical structure 1500. In the vertical structure 1500, PN-junction diodes are formed by the source region 107 and the substrate 109; and the drain region 108 and the substrate 109.
In the model circuit, the PN-junction diodes formed by the source region 107 and the substrate 109 are classified according to the position in the vertical structure. The PN-junction diodes formed by the source region 107 and the substrate 109 are classified into a PN-junction diode 112 on the gate electrode 101 side, a PN-junction diode 114 below the source region 107, and a PN-junction diode 116 on the device isolation region 110 side.
In the model circuit, the PN-junction diodes formed by the drain region 108 and the substrate 109 are classified into PN-junction diodes according to the position in the vertical structure. The drain-side PN-junction diodes are classified into a PN-junction diode 113 on the gate electrode 101 side, a PN-junction diode 115 below the drain region 108, and a PN-junction diode 117 on the device isolation region 110 side.
For a P-channel MOSFET (hereinafter, “PMOS”), the source region 107 and the drain region 108 are P-type regions and a well region is an N-type region. Therefore, in the PMOS, the polarity of each junction diode is the opposite polarity of the PN-junction diodes depicted in FIG. 15.
FIG. 16 is an explanatory diagram of an exemplary equivalent circuit of a conventional NMOS. In an equivalent circuit 1600, “G” denotes the gate electrode 101; “S” denotes a source electrode that is formed in contact with the source region 107; “D” denotes a drain electrode that is formed in contact with the drain region 108; and “B” denotes a substrate electrode that is formed in contact with the substrate 109.
The electrical properties of a PN-junction diode include current and capacitance (hereinafter, “junction leak” and “junction capacitance”, respectively) that are determined according to the voltage between an anode and a cathode, the temperature therebetween, and shape parameters of the portion therebetween. Therefore, a PN-junction diode can be represented by junction capacitance and junction leak.
Hence, in the equivalent circuit 1600, the PN-junction diodes 112 and 113 are respectively represented by a junction capacitance CJGS and a junction leak JLGS; and a junction capacitance CJGD and a junction leak JLGD.
Further, in the equivalent circuit 1600, the PN-junction diodes 114 and 115 are respectively represented by a junction capacitance CJS and a junction leak JLS; and a junction capacitance CJD and a junction leak JLD.
In the equivalent circuit 1600, the PN-junction diodes 116 and 117 are respectively represented by a junction capacitance CJSWS and a junction leak JLSWS; and a junction capacitance CJSWD and a junction leak JLSWD. A substrate resistance Rsub in the equivalent circuit 1600 indicates, as a resistance, the difficulty for current to flow in the substrate 109.
To increase the timing yield of a semiconductor integrated circuit, it is important that delay simulation results for the circuit coincide with actual measurements. Delay in the circuit is significantly influenced by junction capacitance and therefore, accurate replication of the junction capacitance in the simulation is indispensable.
FIG. 17 is an explanatory diagram of an example concerning junction capacitance and junction leak on a gate side of a conventional equivalent circuit. In an equivalent circuit 1700, only the junction capacitances CJGS and CJGD and the junction leaks JLGS and JLGD are depicted. In the equivalent circuit 1700, a gate electrode G, a source electrode S, and a drain electrode D are grounded at a common potential; and a bias Vbs and a small-signal AC power source are disposed between a substrate electrode B and the ground. Substrate resistance Rsub is disregarded because the substrate resistance Rsub is small compared to the junction leaks JLGS and JLGD.
FIG. 18 is an explanatory diagram of an example related to substituting the junction leaks with resistors in a conventional equivalent circuit. In an equivalent circuit 1800, the junction leaks JLGS and JLGD in the equivalent circuit 1700 depicted in FIG. 17 are substituted by junction resistances RJLGS and RJLGD. Although the connection relations and values of coefficients in the equivalent circuit 1700 are defined in the model circuit, such details will not be described and the equivalent circuit 1700 will be described as the model circuit.
Provided the device process is not specialized, the junction capacitances CJGS and CJGD are equivalent and the junction resistances RJLGS and RJLGD are equivalent when Vbs=Vbd. Therefore, it is assumed that equalities CJG=CJGS=CJGD and RJLG=RJLGS=RJLGD are established. According to BSIM 4.6.2, the junction capacitance CJG is expressed as by the equations below.
                    CJG        =                              CJSWGS            ⁡                          (              T              )                                ·                                    (                              1                -                                                      V                    bs                                                        PBSWGS                    ⁡                                          (                      T                      )                                                                                  )                                      -              MJSWGS                                                          (        1        )                                          CJSWGS          ⁡                      (            T            )                          =                  CJSWGS          ·                      [                          1              +                              TCJSWG                ·                                  (                                      T                    -                    TNOM                                    )                                                      ]                                              (        2        )                                          PBSWGS          ⁡                      (            T            )                          =                  PBSWGS          -                      TPBSWG            ·                          (                              T                -                TNOM                            )                                                          (        3        )            
Where, “T” represents the temperature and “TNOM”, “CJSWGS”, “PBSWGS”, “MJSWGS”, “TCJSWG”, and “TPBSWG” are parameters used in the BSIM 4.6.2 (see, e.g., Wenwei (Morgan) Yang, et al, “BSIM 4.6.2 MOSFET MODEL User's Manual”, [online], 2008, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Calif. 94720 [retrieved on Dec. 11, 2009], [URL: http://www.device.eecs.berkeley.edu/{tilde over ( )}bsim3/BSIM4/BSIM462/doc/BSIM462_Manual.pdf]). “CJSWGS(T)” and “PBSWGS(T)” in equation (1) respectively represent equations (2) and (3).
Assuming that the temperature T is, for example, T=TNOM(=room temperature), equation (4) below is obtained by substituting T=TNOM into equation (1).
                    CJG        =                  CJSWGS          ·                                    (                              1                -                                                      V                    bs                                    PBSWGS                                            )                                      -              MJSWGS                                                          (        4        )            
The junction capacitance CJG is conventionally calculated according to equation (4). Admittance, conductance, and susceptance can be expressed as equations (5) to (7) from the equivalent circuit 1800.
                              Y          cnv                =                              G            cnv                    +                      j            ⁢                                                  ⁢                          B              cnv                                                          (        5        )                                          G          cnv                =                              1                          RJLG              s                                +                      1                          RJLG              D                                                          (        6        )                                          B          cnv                =                  ω          ·                      (                                          CJG                s                            +                              CJG                D                                      )                                              (        7        )            
Where, equalities CJG=CJGS=CJGD and RJLG=RJLGS=RJLGD are established. “Ycnv” represents the admittance. “Gcnv” represents the conductance. “Bcnv” represents the susceptance. “CJG” can be represented as equation (8) below from equation (7).
                    CJG        =                              B            cnv                                2            ⁢                                                  ⁢            ω                                              (        8        )            
Actual measurement of the susceptance B/2ω is regarded as measurement of the junction capacitance CJG.
Although not depicted, a region is formed whose impurity concentration is relatively higher than that of the substrate (hereinafter, “intermediate node”), between the source and the drain regions due to a short-channel effect.
Nevertheless, the gate length has become short due to finer scaling, whereby the depletion layer 111 formed by the source region 103 and the substrate 109 and a depletion layer formed by the drain region 104 and the substrate 109 (both depletion layers being formed immediately beneath the intermediate node) may be adjacent to each other or may overlap each other.
When the junction capacitance CJG is calculated according to equation (4) using the equivalent circuit 1800 depicted in FIG. 18 as an input, a problem arises in that the junction capacitance CJG does not coincide with the measured capacitance due to the influence of the depletion layer 111 that spreads out immediately beneath the intermediate node. Therefore, another problem arises in that the accuracy of the simulation is degraded.